1. Field of the Invention
The present invention relates to methods of forming dual damascene openings in which interconnect leads of semiconductor devices are formed.
2. Description of the Related Art
With advances of electronic products, semiconductor technology has been widely applied in manufacturing memories, central processing units (CPUs), liquid crystal displays (LCDs), light emission diodes (LEDs), laser diodes and other devices or chip sets. In order to achieve high-integration and high-speed requirements, dimensions of semiconductor integrated circuits have been reduced and various materials and techniques have been proposed and used to achieve these requirements and overcome obstacles during manufacturing. For example, dual damascene technology and copper are applied to reduce resistances and resistance-capacitance (RC) delay of interconnect structures in integrated circuits. Low-k (low dielectric constant) dielectric materials are required in advanced copper interconnect technology.
FIGS. 1A-1D are schematic cross-sectional views of a prior art method of forming a dual damascene, opening shown step-by-step.
In FIG. 1A, a multi-layer structure is formed. The multi-layer structure includes a silicon nitride layer 110, an oxide layer 120, a nitride layer 130, an oxide layer 140, a silicon oxy-nitride layer 150 and a photoresist layer 160 which are sequentially formed on a substrate 100.
In FIG. 1B, the photoresist layer 160 is patterned to form a trench photoresist opening 170 by a photolithographic process. The oxy-nitride layer is a barrier layer to prevent the photoresist layer 160 from contacting the oxide layer 140, which is a low-k dielectric material layer.
In FIG. 1C, the oxide layer 140 and silicon oxy-nitride layer 150 are patterned to form a trench opening 170a by an etch process with the trench photoresist pattern shown in FIG. 1B. In this etch process, the nitride layer 130 is an etch-stop layer necessary to prevent the oxide layer 120 thereunder from being damaged or etched.
In FIG. 1D, a via hole 180 is formed within the nitride layer 130, the oxide layer 120 and the silicon nitride layer 110. The combination of the trench opening 170a and the via hole 180 provides a dual damascene opening. In this method, the high-k material layers including the silicon oxy-nitride layer 150, the nitride layer 130 and the silicon nitride layer 110 undesirably enhance the capacitances of the interconnect structure. They also raise manufacturing costs of the interconnect structure. It would be desirable to avoid the use of layers with high dielectric constants.
U.S. Pat. No. 6,831,366 provides a low-k dielectric metal conductor interconnect structure. The structure includes at least a multilayer of dielectric materials which are applied sequentially in a single spin apply tool and then cured in a single step and a plurality of patterned metal conductors within the multilayer of spun-on dielectrics. The control over the conductor resistance is obtained by using a buried etch stop layer having a second atomic composition located between the line and via dielectric layers of porous low-k dielectrics having a first atomic composition. The interconnect structure also includes a hard mask which assists in forming the interconnect structure of the dual damascene. The first and second composition are selected to obtain etch selectivity of at least 10 to 1 or higher, and are selected from specific groups of porous low-k organic or inorganic materials with specific atomic compositions and other discoverable quantities.
U.S. Patent Publication No. 2005/0245074 provides a single or dual damascene interconnect structure in the fabrication of semiconductor devices. A via for the interconnect structure is formed by etching an ILD and etch-stop layers in-situ without performing an ashing act therebetween. Then, a patterned resist is ashed in-situ after the resist has been employed in forming the via.
Improved methods of forming a dual-damascene structure are desired. In particular, it would be desirable to etch a trench to a pre-determined stopping point without having to add additional etch stop layers that are undesirable high-k dielectrics.